This relates to pulse generators and more particularly to a circuit to generate periodic pulse trains with a fixed duty cycle.
In electronic systems there is often a need for generating pulse wave forms from sinusoidal or other periodic input signals. This operation is called squaring or clipping. In some applications there is the requirement of having a duty cycle that is a constant and not varying with circuit parameters of active elements, temperature or voltage of input signals. Duty cycle as employed herein is defined as the ratio between the time the output waveform is high and the period of the output waveform.
The importance of this latter requirement is obvious in many digital systems, e.g. in synchronous systems where both edges of the clock are used, and in systems where the pulse train is used to gate out signals of a certain width, as happens in return-to-zero coding in pulse transmission.
Various principles exist for generating square-wave signals from analog signals. Some examples are given in FIGS. 1a, 1b and 1c.
FIG. 1a shows a basic transistor clipper consisting of resistors 1, 2 and 3, transistor 4 and capacitor 5. This circuit is based on saturating and turning off the transistor, and the duty cycle of the output pulses depend strongly upon the amplitude and the waveform of the input signal, the transistor parameters and thus upon temperature.
FIG. 1b shows squaring performed by comparison of the input signal to a reference voltage. This is done by the differentially coupled transistors 11 and 12 and resistors 6, 7, 8, 9 and 10. When the desired duty cycle is 50 percent, and the input signal is symmetrical, this circuit is ideally able to give rather good results. Due to a relatively low gain and interfacing problems, it is often necessary to employ additional amplification stages, which may lead to a deterioration of the duty cycle. Further, if exact duty cycles other than 50 percent is required, the circuit often proves disadvantageous, since the circuit produces output pulse trains whose duty cycle is dependent upon the input signal and the gain of the circuit.
In FIG. 1c a completely different concept is shown. The input signal is passed through a frequency doubler 11, whose output is squared in a low performance squarer 12, whose output is used to trigger a flip-flop 13 in a divide-by-two operation. The output of the flip-flop is pulses with very close to 50 percent duty cycle, the only deterioration is due to a difference in propagation delay between positive and negative transitions of the flip-flop. Furthermore the circuitry very often will be rather complex, and duty cycle other than 50 percent requires even higher complexity.